MichaelValwin/Chipvuelto8
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Fixed some quirks of chip8

Browse Source
This commit is contained in:
Miguel Angel 2024-09-07 01:32:33 +02:00
parent 0b71b99b79
commit 26774f49af
2 changed files with 22 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
index.html
View File

@ -82,7 +82,7 @@
emulator.startAudio(audioContext, volume);
// Load ROM
fetch(fullDirRoms[3])
fetch(fullDirRoms[4])
.then(response => response.arrayBuffer())
.then(arrayBufferRom => {
let romData = new Uint8Array(arrayBufferRom);
@ -93,11 +93,11 @@
setInterval(function() {
if(emulator.isRomLoaded()) {
console.log(emulator.getCPUStatus());
//console.log(emulator.getCPUStatus());
emulator.emulateCycle();
emulator.drawToCanvas(emulatorCanvas, 8);
}
}, 10);
}, 3);
</script>
</body>
</html>

33
src/cpu.ts
View File

@ -228,17 +228,23 @@ class CPU {
}else if(nib4 == 0x1) {
// 8XY1
// Vx |= Vy
this.regs[nib2] |= this.regs[nib3];
this.regs[0xF] = 0;
this.incrementPC();
}else if(nib4 == 0x2) {
// 8XY2
// Vx &= Vy
this.regs[nib2] &= this.regs[nib3];
this.regs[0xF] = 0;
this.incrementPC();
}else if(nib4 == 0x3) {
// 8XY3
// Vx ^= Vy
this.regs[nib2] ^= this.regs[nib3];
this.regs[0xF] = 0;
this.incrementPC();
}else if(nib4 == 0x4) {
// 8XY4
@ -250,23 +256,20 @@ class CPU {
}else if(nib4 == 0x5) {
// 8XY5
// Vx -= Vy
let subs = 0;
if(this.regs[nib2] >= this.regs[nib3]) {
subs = this.regs[nib2] - this.regs[nib3];
}else{
subs = this.regs[nib2] - this.regs[nib3];
//subs = 0xFF - subs;
}
this.regs[0xF] = this.regs[nib2] >= this.regs[nib3] ? 1 : 0;
let subs = this.regs[nib2] - this.regs[nib3];
let carryBit = this.regs[nib2] >= this.regs[nib3] ? 1 : 0;
this.regs[nib2] = subs & 0xFF;
this.regs[0xF] = carryBit;
this.incrementPC();
}else if(nib4 == 0x6) {
// 8XY6
// Vx >>= 1
// Stores the least significant bit of VX prior to the shift in VF
// Then. Shift Vx by 1 to the right.
this.regs[0xF] = this.regs[nib2] & 0x1; // Get the least significat bit
this.regs[nib2] = (this.regs[nib2] >> 1) & 0xFF;
let lsb = this.regs[nib2] & 0x01;
this.regs[nib2] = this.regs[nib3];
this.regs[nib2] = this.regs[nib2] >> 1;
this.regs[0xF] = lsb;
this.incrementPC();
}else if(nib4 == 0x7) {
// 8XY7
@ -280,8 +283,10 @@ class CPU {
// Vx <<= 1
// Set VF to 1 if the most significant bit of VX.
// Then shift to the left Vx
this.regs[0xF] = (this.regs[nib2]) >> 7; // Get msb
this.regs[nib2] = (this.regs[nib2] << 1) & 0xFF;
let msb = this.regs[nib2] >> 7;
this.regs[nib2] = this.regs[nib3];
this.regs[nib2] = this.regs[nib2] << 1;
this.regs[0xF] = msb;
this.incrementPC();
}
@ -431,7 +436,7 @@ class CPU {
// reg_dump(Vx, &I)
// Stores from V0 to VX in memory starting at address I.
for(let i = 0; i <= nib2; i++) {
this.memory[this.indexReg + i] = this.regs[i];
this.memory[this.indexReg++] = this.regs[i];
}
this.incrementPC();
}else if(secondOpcode == 0x65) {
@ -439,7 +444,7 @@ class CPU {
// reg_load(Vx, &I)
// Fills fomr V0 to VX with values from memory staring at address I.
for(let i = 0; i <= nib2; i++) {
this.regs[i] = this.memory[this.indexReg + i];
this.regs[i] = this.memory[this.indexReg++];
}
this.incrementPC();
}